1. Field of the Invention
The present invention relates to a metal-insulator-metal (MIM) capacitor and a method of fabricating the same, and more particularly, to an MIM capacitor capable of preventing the generation of a crack around the edges of a dielectric layer and a method of fabricating the MIM capacitor.
2. Description of the Related Art
Semiconductor devices in BIPOLAR, BICMOS and CMOS technology require integrated capacitors having high voltage linearity, accurately settable capacitance values, and low parasitic capacitance values. Conventional MOS or MIS capacitors commonly employed in contemporary systems not only have unsatisfactory voltage linearity that arises from voltage-induced space charge regions but also numerous sources of parasitic capacitance.
To avoid theses difficulties, polysilicon-insulator-polysilicon (PIP) capacitors have recently become popular. However, since the PIP capacitors use conductive polysilicon for an upper electrode layer and a lower electrode layer, an oxidation reaction occurs in the interfaces between upper and lower electrodes and a dielectric layer, resulting in the formation of a natural oxide film and thus reduction of the overall capacitance value.
One approach to solving this problem is to use metal-insulator-metal (MIM) capacitors that are primarily used for storing charge in various semiconductor devices such as mixed-signal devices and analog devices.
FIG. 1 is a cross sectional view of a conventional metal-insulator-metal (MIM) capacitor. As shown in FIG. 1, a conventional MIM capacitor 10 includes a lower electrode layer 100, a dielectric layer 110, an upper electrode pattern 150 including a first upper electrode pattern 120 and a second upper electrode pattern 130, and an upper interconnect 180. The dielectric layer 110 is formed in an opening 107 of an interlayer insulating layer 130, on the lower electrode layer 100 and has sidewalls, and a bottom of the dielectric layer 110 is in contact with the lower electrode layer 100. The upper electrode pattern 150 is conformally formed on the dielectric layer 110. The interlayer insulating layer 105 covers the entire surface of the resulting structure formed on the lower electrode layer 100 and upper surfaces of the sidewalls of the dielectric layer 110 and an upper surface of the upper electrode layer 120 remain exposed. The upper interconnect 180 is conformally formed on the upper electrode pattern 150 and the interlayer insulating layer 105.
In this case, the upper electrode pattern 150 includes the first upper electrode pattern 120 made of TiN and the second upper electrode pattern 130 made of tungsten (W). The upper interconnect 180 is made of aluminum (Al).
In the case of the MIM capacitor illustrated in FIG. 1, since the entire thickness of the upper electrode pattern 150 formed within the opening 107 formed within the interlayer insulating layer 105 is thinner than that of the interlayer insulating layer 105, a part of the opening 107 is filled with the upper electrode pattern 150, and the remainder of the opening 107 is filled with the upper interconnect 180. In other words, Al forming the upper interconnect 180 and the second upper electrode pattern 130 of the upper electrode pattern 150 coexist within the opening 107. However, Al forming the upper interconnect 180 and W forming the second upper electrode pattern 130 have different coefficients of thermal expansion, and thus, stress is concentrated around the edges 155 of the second upper electrode pattern 130, which are bent into an “L”-shape since Al forming the upper interconnect 180 swells in the subsequent thermal treatment process after forming the upper interconnect 180. As a result, cracks can be generated in the dielectric layer 110 that contacts the edges 155 of the upper electrode pattern 150, thereby lowering the overall manufacturing yield of MIM capacitors.